1. Field of the Invention
This invention relates to a dynamic semiconductor memory device.
2. Description of the Related Art
Dynamic semiconductor memory devices (hereinafter, referred to as DRAMs) with a one-transistor/one-capacitor memory-cell structure have recently had a much larger density as a result of improvements in the memory cell structure and advances in submicroscopic processing technology. The design rules for wires including bit lines and word lines, and transistors, have therefore been reduced. The method of arranging memory cells and sense amplifier blocks is one of the major design requirements that determine the area of a DRAM or its performance.
Already proposed methods of constructing a cell array containing memory cells and sense amplifier blocks will be explained briefly below.
For sense amplifier systems for DRAMs, an open bit-line architecture is used for up to 16 Kbits, and a folded bit line architecture is used for the generations of 16 Kbits to present 64-Mbits.
FIG. 1A shows a method of constructing a DRAM known as an open bit line architecture. Memory cells MC are arranged at all intersections where word lines WL cross bit lines BL. This arrangement maximizes the density of memory cells and is suitable for obtaining a chip with a small area. With this method, if the design minimum size is F, the theoretical cell area will be 4F.sup.2.
In a layout design of a sense amplifier block, sense amplifier blocks SA must be placed on a 1BL. pitch, making the design rules for sense amplifier blocks SA very strict. Because bit line pairs are in different cell arrays, noise generated in a cell array is introduced onto only one of the bit-line pair. Since the noise is difficult to cancel, the arrangement is less immune to noise. Furthermore, memory cells are connected to all of the intersections of bit lines and word lines and the bit-line capacity per word line is large, it is impossible to make the number of word lines very large. As a result, the number of sense amplifiers within the chip is large, thus preventing the chip size from being made smaller as expected.
FIG. 1B shows a method of constructing a DRAM known as a relax open bit line architecture. In this method, memory cells MC are placed at all intersections of word lines WL and bit lines BL with one sense amplifier block SA for every two BLs. The layout of the sense amplifier block SA is easier to design than by the open bit line architecture. The former, however, is not satisfactory. Furthermore, the relax open bit-line architecture is liable to noise as is the open bit-line architecture. In addition, it has a large bit-line capacity per word line.
FIG. 1C shows a method of constructing a DRAM known as a folded bit-line architecture. In this method, sense amplifier blocks SA are placed on a 4-BL pitch. Therefore, layout design of a DRAM is relatively easier to design than by the open bit-line architecture. Because in the folded bit line architecture, bit-line pairs are formed within a single cell array, noise generated within the array is introduced onto both of each pair, making the DRAM immune to noise.
With the folded bit-line architecture, if the minimum size is F, the area of a memory cell will be 8F.sup.2. Thus, the area of a memory cell is twice as large as that of the open bit-line architecture, resulting in an increase in the chip area.
As mentioned above, the design rules for sense amplifier blocks are less strict for the open bit-line architecture, the relax open bit-line architecture, and the folded bit line architecture in that order. The chip area is greater because of increasing the memory cell area. Namely, the design rules for sense amplifier blocks are made less strict by changing the sensing method, resulting in so much an increase in the chip area.
Additionally, with conventional DRAMs, the folded bit line architecture makes the DRAM more immune to noise, but cannot make the memory size smaller. In contrast, the open bit line architecture makes the memory size smaller, but cannot make the DRAM more immune to noise.